Technical Field
The present disclosure relates to a memory device. More particularly, the present disclosure relates to a memory controller and a control method thereof.
Description of Related Art
Flash memory devices have been widely utilized. In general, a memory device is configured to a have a memory controller for controlling multiple flash memory dies of multiple channels.
Generally speaking, the memory controller is required to assert another access command corresponding to a flash memory die after a current access command on the flash memory die is ended. Moreover, at any specific point in time, the memory controller is only able to make one of the multiple flash memory dies in the same channel transmit data. In some approaches, the memory controller is configured to make the flash memory dies in the same channel enter a busy status at the same time. However, due to the limitation of the memory controller discussed above, and with the increase in data throughput of a processor coupled to the memory device, it is difficult to make the flash memory dies in the same channel enter the busy status at the same time. As a result, the data transmission efficiency is reduced.